1. Field of the Invention
The present invention relates to the field of integrated circuit drivers used in digital systems. More particularly, the present invention relates to the field of bootstrapped, bipolar integrated circuit drivers capable of fast response times in connection with large capacitive loads.
2. Prior Art
In order to drive the clock circuits of digital circuitry, or more particularly the clock inputs of an N-channel MOS random access memory, it is necessary to provide a driver having a fast response and a high logic level output voltage which is as close as possible to the voltage of the integrated circuit power supply. Typically, this means a high logic level output voltage from the driver within one volt of the power supply voltage. However, in practical applications an even greater logic level output signal is required because of power supply noise, unavoidable ohmic drops, parasitic coupling, circuit noise and inductive ringing. The combined effect of these perturbations typically requires a high logic level output voltage from the driver within 0.5 volts or less of the power supply voltage. In addition, these high logic level outputs must be delivered within short time intervals to large capacitive loads which are characterized by large transient current demands.
The prior art driver circuits which are designed to meet the above output performance criteria have been subject to several inherent disadvantages. Such prior art driver circuits have included a bipolar device operated in the emitter follower mode. In order to operate a bipolar, npn device in the emitter follower mode it is necessary to forward bias the base-emitter junction by voltage, Vbe, typically in the range of 0.6 to 0.9 volts. In addition, the emitter current is proportional to the base current, which in turn must flow through a biasing resistor coupled to the power supply. For example, FIG. 1 (a) illustrates one of the simpler prior art inverting drivers. In this prior art circuit a high logic level input signal to the base of transistor 10 causes transistor 10 to conduct. This in turn causes transistor 14 to conduct and thereby to act as a sink and draw the charge on the output node to ground. However, when a low logic level input signal is applied to the base of transistor 10, transistor 10 will turn off. As a result, the voltage at the base of transistor 12 will begin to approach that of the power supply. Nevertheless, the maximum output voltage applied to the output node will never be higher than the supply voltage, Vdd, minus the voltage drop from the base to emitter drop of transistor 12. Thus, the voltage of the output node will approach Vdd - Vbe (12). As the output voltage approaches Vdd - Vbe (12), the amount of base drive on transistor 12 will decrease and the amount of current flowing through transistor 12 will begin to decrease. Typically, the driver of FIG. 1 will tend to be current limited when coupled to a high capacitive load since the drive transistor 12 will fall off before sufficient current has outputted. In addition, because of the rapid decrease of the base drive of transistor 12, the output rise time of the driver will be substantially degraded when current limitation occurs.
In order to remedy the deficiencies of the prior art circuit of FIG. 1(a), the prior art has replaced transistor 12 by a Darlington pair, transistors 16 and 18 (FIG. 1b). The base drive of transistor 16 is now supplied by the additional gain provided by transistor 18. Thus the rise time of the high logic level output is substantially decreased as compared to that of the driver circuit of FIG. 1(a). Nevertheless, the current flowing through transistor 16 will substantially decrease when the output voltage approaches Vdd - Vbe (16). At this point the current requirements of the output will have to be provided by current flowing through transistor 16 and resistor 34. Thus, as mentioned above the base drive of transistor 16 will then substantially decrease as the base voltage approaches the supply voltage and a substantial degradation of the output rise time results.
In order to provide a driver circuit not subject to current limitation, the prior art has modified the circuit of FIG. 1(a) by employing a complementary, saturated output transistor in combination with transistor 20 (FIG. 1(c)). In this prior art circuit, when a low logic level signal is applied to the base of transistor 10, transistor 10 is turned off. The voltage on the base of transistor 20 then rises towards the supply voltage, turning it on, and causing the biased transistor 22 to go into saturation. However, the circuit of FIG. 1(c) is not a practical monolithic design since standard or even exotic bipolar semiconductor processes are not presently available to permit the fabrication on a single chip of a high speed, high current pnp transistor and a high speed, high current npn transistor. Therefore, the prior art has used the driver circuit of FIG. 1(c) wherein the complementary, saturated transistor 22 is an external, discrete device. Such a design has the obvious disadvantages of higher cost and greater bulk. These factors decrease the number of drivers which may be encapsulated in a single package and therefore substantially decrease the device density on system cards.
Another attempt of the prior art to provide a high speed driver which is not subject to current limitation is accomplished by the use of two high voltage power supplies. (FIG. 1(d)). The circuit of FIG. 1(b) may be altered as shown in FIG. 1(d) by coupling the collectors of each transistor of the Darlington pair, i.e. 24 and 26, to a separate high voltage power supply. Therefore, if Vdd2 is greater than Vdd, the base of transistor 24 will tend to approach a greater voltage, thus impressing a higher voltage upon the second transistor 26 of the Darlington pair. As a result the output voltage may rise to a level much closer to the supply voltage, Vdd, before transistor 26 becomes current limited. Clearly, the disadvantages of having separate power supplies includes a higher system cost entailed by the additional supply, additional space required to house the second supply, and an extra power supply bus which must be wired to and provided on many of the cards of the system.